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MC100EP139
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/2/4, /4/5/6
Clock Generation Chip
The MC100EP139 is a low skew /2/4, /4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the /2/4 and the /4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation.
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TSSOP-20 DT SUFFIX CASE 948E
SO-20 DW SUFFIX CASE 751D
MARKING DIAGRAM
KEP 139 ALYW
MC100EP139 AWLYWW
A L Y W
= Assembly Location = Wafer Lot = Year = Work Week
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week
* * * * * * * * * * * *
50ps Output-to-Output Skew PECL mode: 3.0V to 5.5V VCC with VEE = 0V ECL mode: 0V VCC with VEE = -3.0V to -5.5V Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips Q Output will default LOW with inputs open or at VEE ESD Protection: >2KV HBM, >100V MM VBB Output New Differential Input Common Mode Range Moisture Sensitivity Level 2 For Additional Information, See Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 758 devices
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC100EP139DT MC100EP139DTR2 MC100EP139DW MC100EP139DWR2 Package TSSOP TSSOP SOIC SOIC Shipping 75 Units/Rail 2500 Tape/Reel 38 Units/Rail 2500 Tape/Reel
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
(c) Semiconductor Components Industries, LLC, 1999
1
December, 1999 - Rev. 1
Publication Order Number: MC100EP139/D
MC100EP139
VCC 20 Q0 19 Q0 18 Q1 17 Q1 16 Q2 15 Q2 14 Q3 13 Q3 12 VEE 11
1 VCC
2 EN
3 DIVSELb0
4 CLK
5 CLK
6 VBB
7 MR
8 VCC
9 DIVSELb1
10 DIVSELa FUNCTION ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff /2/4 Outputs ECL Diff /4/5/6 Outputs ECL Freq. Select Input ECL Freq. Select Input
Figure 1. 20-Lead SOIC (Top View)
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
FUNCTION TABLES
CLK Z ZZ X EN L H X MR L L H FUNCTION Divide Hold Q0:3 Reset Q0:3 PIN CLK, CLK EN MR VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa DIVSELb0 Q2:3 OUTPUTS Divide by 4 Divide by 6 Divide by 5 Divide by 5 DIVSELb1 VCC VEE
PIN DESCRIPTION
Z = Low-to-High Transition ZZ = High-to-Low Transition
DIVSELa 0 1
Q0:1 OUTPUTS Divide by 2 Divide by 4
DIVSELb0 DIVSELb1 0 1 0 1 0 0 1 1
B2/4 B4/5/6 ECL Freq. Select Input B4/5/6
ECL Positive Supply ECL Negative, 0 Supply
DIVSELa Q0 CLK CLK /2/4 R Q0 Q1 Q1
EN
Q2 /4/5/6 R Q2 Q3 Q3
MR DIVSELb0 DIVSELb1
Figure 2. Logic Diagram
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MC100EP139
CLK Q (/2) Q (/4) Q (/5) Q (/6)
Figure 3. Timing Diagram
CLK tRR RESET
Q (/n)
Figure 4. Timing Diagram
MAXIMUM RATINGS*
Symbol VEE VCC VI VI Iout IBB TA Tstg JA (DT Suffix) JC (DT Suffix) JA (DW Suffix) JC (DW Suffix) Tsol Power Supply (VCC = 0V) Power Supply (VEE = 0V) Input Voltage (VCC = 0V, VI not more negative than VEE) Input Voltage (VEE = 0V, VI not more positive than VCC) Output Current VBB Sink/Source Current{ Operating Temperature Range Storage Temperature Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Solder Temperature (<2 to 3 Seconds: 245C desired) Still Air 500lfpm Still Air 500lfpm Continuous Surge Parameter Value -6.0 to 0 6.0 to 0 -6.0 to 0 6.0 to 0 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 5% 90 60 33 to 35 5% 265 Unit VDC VDC VDC VDC mA mA C C C/W C/W C/W C/W C
* Maximum Ratings are those values beyond which damage to the device may occur. { Use for inputs of same package only.
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MC100EP139
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = -5.5V to -3.0V) (Note 3.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current (Note 1.) Output HIGH Voltage (Note 2.) Output LOW Voltage (Note 2.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 70 -1250 -1995 Typ 85 -1100 -1850 -1022 -1642 150 0.5 -150 Max 100 -895 -1650 Min 70 -1250 -1995 25C Typ 90 -1100 -1850 -1022 -1642 150 0.5 -150 Max 105 -895 -1650 Min 75 -1250 -1995 85C Typ 95 -1100 -1850 -1022 -1642 150 Max 110 -895 -1650 Unit mA mV mV mV mV A A
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating. 2. All loading with 50 ohms to VCC -2.0 volts. 3. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVPECL (VCC = 3.3V 0.3V, VEE = 0V) (Note 6.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current (Note 4.) Output HIGH Voltage (Note 5.) Output LOW Voltage (Note 5.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 70 2050 1305 Typ 83 2200 1450 2277 1657 150 0.5 -150 Max 100 2405 1650 Min 70 2050 1305 25C Typ 87 2200 1450 2277 1657 150 0.5 -150 Max 105 2405 1650 Min 75 2050 1305 85C Typ 90 2200 1450 2277 1657 150 Max 110 2405 1650 Unit mA mV mV mV mV A A
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 4. VCC = 3.0V, VEE = 0V, all other pins floating. 5. All loading with 50 ohms to VCC -2.0 volts. 6. Input and output parameters vary 1:1 with VCC.
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MC100EP139
DC CHARACTERISTICS, PECL (VCC = 5.0V 0.5V, VEE = 0V) (Note 9.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current (Note 7.) Output HIGH Voltage (Note 8.) Output LOW Voltage (Note 8.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 70 3750 3005 Typ 85 3900 3150 3977 3357 150 0.5 -150 Max 100 4105 3350 Min 70 3750 3005 25C Typ 90 3900 3150 3977 3357 150 0.5 -150 Max 105 4105 3350 Min 75 3750 3005 85C Typ 95 3900 3150 3977 3357 150 Max 110 4105 3350 Unit mA mV mV mV mV A A
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 7. VCC = 5.0V, VEE = 0V, all other pins floating. 8. All loading with 50 ohms to VCC -2.0 volts. 9. Input and output parameters vary 1:1 with VCC.
AC CHARACTERISTICS (VCC = 3.0V to 5.5V; VEE = 0V) or (VCC = 0V; VEE = -3.0V to -5.5V)
-40C Symbol fmax tPLH, tPHL tSKEW tJITTER tr tf ts th Vpp trr tpw Characteristic Maximum Toggle Frequency (Note 10.) Propagation Delay CLK, Q(DIFF) CLK, Q(SE) MR, Q Q, Q TBD Q, Q 110 200 400 100 150 300 180 120 50 800 1200 250 125 200 400 100 150 300 Min 1.0 550 Typ 1.2 700 800 Max Min 1.0 600 25C Typ 1.2 750 900 Max Min 1.0 675 85C Typ 1.2 825 975 Max Unit GHz ps
Device Skew Part-to-Part (Note 11.) Cycle-to-Cycle Jitter Output Rise and Fall Times (20% - 80%) Setup Time Hold Time
50 200 TBD 190 120 50 800 100 1200 275 150 200 400 100 150 300 TBD 215 120 50 800 1200 300
ps ps ps ps ps mV ps 550 450 ps
EN, CLK DIVSEL, CLK CLK, EN CLK, DIVSEL
Input Voltage Swing (Diff) Reset Recovery Time Minimum Pulse Width CLK MR
550
450
550
450
10. Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only. 11. Skew is measured between outputs under identical transitions.
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MC100EP139
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1 J J1
B L
PIN 1 IDENT 1 10
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E
2X
L/2
20
11
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC100EP139
PACKAGE DIMENSIONS
SO-20 DW SUFFIX 20 PIN PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
h
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
DIM A A1 B C D E e H h L
L
18X
e
A1
q
T
C
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MC100EP139
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC100EP139/D

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